RMC VLSI Laboratory

Research and Graduate Studies Electrical and Computer Engineering

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Recent Publications

Journal Papers

  • A. Kabbani, D. Al-Khalili, A.J. Al-Khalili, Delay Analysis of CMOS Gates Using Modified Logical Effort Model, submitted to the IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems.
  • H. Saaied, D. Al-Khalili, A.J. Al-Khalili and M. Nekili, Simultaneous Adaptive Wire Adjustment and Local Topology Modification for Tuning a Bounded Skew Clock, submitted to the IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems.
  • A. Kabbani, D. Al-Khalili and A.J. Al-Khalili, Technology Portable Analytical Model for DSM CMOS Inverter Delay Estimation, IEE Proceedings on Circuits, Devices and Systems, in print.
  • J.M.P. Langlois and D. Al-Khalili, Carry-free approximate squaring functions with O(n) complexity and O(1) delay, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, in print.
  • J.M.P. Langlois and D. Al-Khalili, Phase to Sinusoid Amplitude Conversion Techniques for Direct Digital Frequency Synthesis, IEE Proceedings on Circuits, Devices and Systems, in print.
  • J.Coppens, D. Al-Khalili and C.Rozon, VHDL Modelling and Analysis of Fault Secure Systems for ASICs Accepted for publication at the SCS Simulation Journal, Special Issue on the Role of Simulation in Design Automation of VLSI Circuits and Systems.
  • D. Shaw, D. Al-Khalili and C. Rozon, ASIC Bridge Fault Modeling with Neural Network-Based VHDL Saboteurs, IEEE Transactions on Computers, Volume: 52, Issue: 10, Oct. 2003, pp.1285 – 1297.
  • K. Yip and D. Al-Khalili, Multi-level Logic Synthesis Using Hybrid Pass Logic and CMOS Topologies IEE Proceedings on Circuits, Devices and Systems, Vol. 150, No. 5, October 2003, pp. 445-452.
  • J.M.P. Langlois and D. Al-Khalili, Novel approach to the design of direct digital frequency synthesizers based on linear interpolation, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 50, no. 9, September 2003, pp. 567-578.
  • Kabbani, D. Al-Khalili, A.J. Al-Khalili, Technology Portable Analytical Model for DSM CMOS Inverter Transition Time Estimation, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Volume: 22, Issue: 9, Sept. 2003, pp.1177 – 1187.
  • J.M.P. Langlois, D. Al-Khalili, and R.J. Inkol, Polyphase filter approach for high performance, FPGA-based quadrature demodulation, The Journal of VLSI Signal Processing Systems, vol. 32, no.3, November 2002, pp. 237-254.
  • D. Shaw, D. Al-Khalili, C. Rozon, Fault Security Analysis of CMOS VLSI Circuits Using Defect Injectable VHDL Models, Integration, the VLSI Journal, 32 (2002), pp77-79.
  • R. Pillai, D. Al-Khalili and A.J. Al-Khalili and S.Y.A Shah, Low Power Approach to Floating Point Adder Design for DSP applications, Journal of VLSI Signal Processing, Vol. 27, pp.195-213, March 2001.
  • R. Pillai, D. Al-Khalili, A. Al-Khalili, Low Power Architecture for Floating Point MAC Fusion, IEE Proceedings, Computers and Digital Techniques, July 2000, Vol. 147, Issue 4, pp. 288.
  • M. Gallant and D. Al-Khalili, Synthesis of Low Power CMOS Circuits Using Hybrid Topologies, Integration, the VLSI Journal 27 (1999) pp143-163.

Conference Papers

2004
  • H. Saaied, D. Al-Khalili, A. Al-Khalili, Clock Tree Routing using Shortest Paths Polygon, Accepted at the IEEE International SoC Conference, Sept. 12-14, 2004, Santa Clara, California 2004
  • J, Xue, D. Al-Khalili, C. Rozon, A Normalized Intrinsic Delay Model of Static CMOS Complex Gate for Deep Sub-micron Technologies, Proceedings of the Northeast Workshop on Circuits and Systems, NEWCAS04, Montreal, June 2004.
  • A. Kabbani, D. Al-Khalili, A. Al-Khalili, Technology Portable Delay Model for DSM CMOS Inverters, Proceedings of the Northeast Workshop on Circuits and Systems, NEWCAS04, Montreal, June 2004.
  • J.M.P. Langlois, D. Al-Khalili and H. Al-Hertani, Carry free, bit parallel approximate squarers with linear complexity and constant delay, in Proceedings of the IEEE Northeast Workshop on Circuits and Systems, Montréal, QC, June 2004, pp. 385-388.
  • J.M.P. Langlois, Design of Linear Phase FIR Filters using Particle Swarm Optimization, in Proceedings of the Queen's Biennial Symposium on Communications, Kingston, ON, May 2004, pp. 172-174.
2003
  • H. Saaied, D. Al-Khalili, A. Al-Khalili, Simultaneous Topology Optimization and Delay-Cost Minimization of High Performance Nets with Obstacle Constraints, Proceedings of the 46th IEEE International Midwest Symposium on Circuits and Systems, Midwest 04, Cairo, Egypt, December 2003.
  • A. Kabbani, D. Al-Khalili, A. Al-Khalili, Technology Portable Analytical Model for DSM CMOS Inverter Transition Time Estimation, Proceedings of the 46th IEEE International Midwest Symposium on Circuits and Systems, Midwest 04, Cairo, Egypt, December 2003.
  • H. Saaied, D. Al-Khalili, A. Al-Khalili, Area Minimization of Clock Distribution Networks Using Local Topology Modification, Proceedings of the 2003 IEEE International SoC Conference, Oregon, September 17-20, 2003.
  • H. Saaied, D. Al-Khalili, A. Al-Khalili, Adaptive Wire Adjustment and Local Topology Modification for Tuning Bounded Skew Clock Distributed Networks, Proceedings of the Northeast Workshop on Circuits and Systems, NEWCAS03, Montreal, June 2003
  • H. Saaied, D. Al-Khalili, A. Al-Khalili and M. Nekili, Adaptive Wire Adjustment for Bounded Skew clock distribution network, Proceedings of the ASP-DAC 2003: Asia and South Pacific Design Automation Conference, Kitakyushu International Conference Center, Kitakyushu, Japan.
  • J.M.P. Langlois and D. Al-Khalili, Low power direct digital frequency synthesizers in 0.18 m m CMOS, in Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, CA, September 2003, pp. 283-286.
  • J.M.P. Langlois and D. Al-Khalili, Piecewise continuous linear interpolation of the sine function for direct digital frequency synthesis, in Proceedings of the IEEE Radio Frequency Integrated Circuits Symposium, Philadelphia, PA, June 2003, pp. A65-A68.
  • Q. Liu, J.M.P. Langlois, D. Al-Khalili, V. Szwarc and R. Inkol, Synthesis of a 12-bit complex mixer for FPGA implementation, in Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering, Montréal, QC, May 2003, pp. 81-84.
  • K. Yip and D. Al-Khalili, Multi-Level Logic Synthesis Using Hybrid Pass Logic and CMOS Topologies, Proceedings of the 11th the Iranian Conference in Electrical Engineering ICEE03, Shiraz, Iran, May 2003.
2002
  • Saaied, D. Al-Khalili, A. Al-Khalili and M. Nekili, Quadratic deferred-merge embedding algorithm for zero skew clock distribution network, Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU) Monterey, CA., November. 2002.
  • H. Saaied, D. Al-Khalili, A. Al-Khalili and M. Nekili, Adaptive Wire Adjustment for Zero Skew Clock Distribution Network Using Quadratic Tree, Proceedings of the ICM 14th International Conference on Microelectronics, Beirut, December 2002.
  • J.M.P. Langlois and D. Al-Khalili, A quadrature direct digital frequency synthesizer architecture using piecewise-continuous linear segments, in Proceedings of the Queen's Biennial Symposium on Communications, Kingston, Ontario, June 2002, pp. 463-467.
  • J.M.P. Langlois and D. Al-Khalili, A new approach to the design of low power direct digital frequency synthesizers, in Proceedings of the IEEE International Frequency Control Symposium, New Orleans, Louisiana, May 2002, pp. 654-661.
  • J.M.P. Langlois and D. Al-Khalili, Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purity, in Proceedings of the IEEE International Symposium on Circuits and Systems, Phoenix, Arizona, May 2002, pp. 361-364.
  • J.M.P. Langlois and D. Al-Khalili, A low power direct digital frequency synthesizer with 60 dBc spectral purity, in Proceedings of the ACM Great Lakes Symposium on VLSI, New York, NY, April 2002 , pp. 166-171.
2001
  • D. Shaw, Dhamin Al-Khalili and C. Rozon, Accurate CMOS Bridge Fault Modeling With Neural Network-Based VHDL Saboteurs, Proceedings of ICCAD 2002, San Jose, California, 4-8 November 2001.
  • D. Shaw, D. Al-Khalili, and C. Rozon, Automated Defect to Fault Translation for ASIC Standard Cell Libraries, Proceedings of the 2001 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Victoria BC, 26-28 August, 2001.
  • R. Pillai, S.Y.A. Shah, A.J. Al-Khalili and D. Al-Khalili, Low Power Floating Point MAF's- A Comparative Study, Proceedings of the 6th IEEE International Symposium on Signal Processing and its Applications, Kuala Lumpur, Malaysia, 13th -16th August, 2001
  • D. Shaw, D. Al-Khalili, C. Rozon, Deriving Accurate ASIC Cell Fault Models for VITAL Compliant VHDL Simulation Proceedings of the IEEE International Symposium on Circuits and Systems, May 2001, Sydney, Australia.
  • J.M.P. Langlois and D. Al-Khalili, Efficient sine amplitude computation for direct digital frequency synthesis, in Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, Cairo, Egypt, December 2001.
  • J.M.P. Langlois and D. Al-Khalili, ROM size reduction with low processing cost for direct digital frequency synthesis, in Proceedings of the 2001 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Victoria BC, 26-28 Aug. 2001, pp. 287-290.
2000
  • J. Costello and D. Al-Khalili, Behavioral Synthesis of Low Power Floating Point CORDIC Processors, Proceedings of the IEEE International conference on Electronics, Circuit and Systems, ICECS2K, December 2000, Lebanon
  • P.Sun, A. Al-Khalili and D. Al-Khalili, A CAD Tool for First Hand CMOS Circuit Selection, Proceedings of the IEEE International conference on Electronics, Circuit and Systems, ICECS2K, December 2000, Lebanon.
  • C. Rozon, D. Al-Khalili, S. Adham and D. Racz, Comparing Defect Coverage for Current-Mode Logic and CMOS VLSI Cells, Proceedings of the IEEE International conference on Electronics, Circuit and Systems, ICECS2K, December 2000, Lebanon.
  • S. Adham, D. Al-Khalili, C. Rozon and D. Racz, Comprehensive Defect Analysis and Testability of Current Mode Logic, The 2000 IEEE International Symposium on Circuits and Systems (ISCAS 2000), Geneva, Switzerland, May 28-31, 2000, pp 339-342
  • J.M.P. Langlois, D. Al-Khalili, and R.J. Inkol, Polyphase filter approach for high performance, FPGA-based quadrature demodulation in Proceedings of DSP-Deutschland, Munich, 11-12 October 2000, pp. 243-250.
1999
  • R. Pillai, D. Al-Khalili and A.J. Al-Khalili, An IEEE Compliant Floating Point MAF, Proceedings of the X IFIP VLSI Conference, Portugal, December 1999.
  • R. Pillai, D. Al-Khalili and A.J. Al-Khalili, Power Implications of Additions in Floating Point DSP-an Architectural Perspective, Proceedings of the Africon'99, September 1999.
  • R. Pillai, D. Al-Khalili and A.J. Al-Khalili, Power Implications of Precision Limited Arithmetic in Floating Point FIR Filters, Proceedings of the IEEE International Conference on Circuits and Systems, Orlando, May 1999.
  • J.M.P. Langlois, D. Al-Khalili, and R.J. Inkol, A high performance, wide bandwidth, low cost FPGA-based quadrature demodulator, in Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering, Edmonton AB, 9-12 May 1999, pp. 497-502.
  • R. Pillai, D. Al-Khalili and A. Al-Khalili, Arithmetically Sub-optimal Floating Point Digital Filters- an Architectural Power Perspective, Proceedings of the 1999 IEEE Canadian Conference in ECE, EECEC'99, Edminton, May 9-12, 1999.
1998
  • M. Gallant and D. Al-Khalili, Synthesis of Low Power Circuits Using Combined Pass Logic and CMOS Topologies, Proceeding of the International Conference of Microelectronics, ICM'98, Monastir, December 1998.
  • R. Pillai, D. Al-Khalili and A. Al-Khalili, On the Power Implications of Floating point Addition in IIR Filters, Proceedings of the International Conference of Microelectronics, ICM'98, Monastir, December 1998.
  • D. Al-Khalili, S. Adham, C. Rozon, M. Hossain and D. Racz, Comprehensive Defect Analysis and Defect Coverage of CMOS Circuits, Proceedings of the 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT'98, Austin, Texas, November 1998.
  • J.Coppens, D. Al-Khalili and Come Rozon, VHDL Modelling and Analysis of Fault Secure Systems, Proceedings of the Design Automation and Test in Europe, DATE '98, Paris, France, March 1998.
  • R. Pillai, D. Al-Khalili and A.J. Al- Khalili,A Low Power Floating Point Accumulator, Proceeding of IEEE Conference on VLSI Design'98: VLSI for Signal Processing, Chennai, India, and January 1998.
  • R. Pillai, D. Al-Khalili and A. Al-Khalili, Low Power Conditional Sum Adder Using Pass Logic Topology, Proceedings of the IEEE 1998 Canadian Conference on Electrical and Computer Engineering, CCECE'98, Waterloo, Ontario May, 1998.
  • R. Pillai, D. Al-Khalili and A. Al-Khalili, On the Distribution of Exponent Differences During Floating Point Addition, Proceedings of the IEEE 1998 Canadian Conference on Electrical and Computer Engineering, CCECE'98, Waterloo, Ontario May 1998.

Book Chapters

  • R. Pillai, D. Al-Khalili, A.J. Al-Khalili, An IEEE Compliant Floating Point MAF, one section in a book entitled VLSI Systems on Chip, Kluwer Academic Publishers, ISBN 0-7923-7731-1, December 99.

Patents, Technical Reports and Others

  • J.M.P. Langlois and D. Al-Khalili, Phase to sine amplitude conversion system and method, U.S. patent 6,657,573, 2 December 2003.
  • D. Shaw, D. Al-Khalili and C. Rozon, Methods and Apparatus for Simulating the Effects of Bridge Defects in Integrated Circuits, Provisional Patent Application, September 2001.
  • J.M.P. Langlois, A low power direct digital frequency synthesizer with 60 dBc spectral purity realized in 0.18 m m CMOS, presented at the Symposium on Microelectronics Research & Development in Canada), Ottawa, Ontario, June 2002.
  • J.M.P. Langlois, D. Al-Khalili and R.J. Inkol, A conceptual framework for high performance FPGA-based digital quadrature demodulation, presented at the Technical Cooperation Program, Electronic Warfare Systems, Technical Panel 4, Ottawa, Ontario, September 2001.
  • D. Shaw, D. Al-Khalili and C. Rozon, Fault Security Analysis Project FSA Software Package and Preliminary Results, 11 March 1999 CSE 20.
  • D. Racz, D. Al-Khalili and C. Rozon, Automated Fault Analysis of Standard Process Report, with C. Rozon and D. Racz, CSE-19 Submitted to CSE, 31 July 1998.
  • D. Shaw, D. Al-Khalili and C. Rozon, Fault Security Analysis Project: Software Integration and User Interface, CSE-16, 8 February 1998.